The background description provided here is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
High-resolution digital-to-analog converters (DACs) suffer from high component count and area penalty. One approach to lower the high component count and area penalty is to segment the DAC such that a primary DAC converts the most significant bits of data and a sub-DAC converts the least significant bits of the data. Outputs of the primary and sub-DACs are combined to generate the output of the combined DAC. The sub-DAC must be linear only to the least significant bit level allowing a reduction in the size requirement of the sub-DAC. Any reduction in the sub-DAC component count and area reduces the overall DAC component count and area. The sub-DAC, however, loads the primary DAC, causing linearity errors, glitches, and cross-talk. In some sub-DAC architectures, linearity errors can be removed, but glitches and cross-talk remain due to capacitive loading. Minimizing the sub-DAC capacitive loading on the primary DAC reduces these errors.